FIG. 1 shows a prior art phase lock loop 100 which uses an early/late gate phase detector scheme. The operation of the early/late gate phase detector in a phase lock loop is documented in Gardner's book titled "Phaselock Techniques" 2d Edition on pages 235-241. A data bit stream is applied to an input terminal 101 of an early/late gate phase detector. The early/late gate phase detector includes a pair of gated integrators 102, 104. Each of the gated integrators alternately integrates an input data signal over one-half of a time interval T/2, where T is the bit time interval. Integration is performed by the early gated integrator 102 just prior to a bit transition and by the late gated integrator 104 just after a data bit transition. Each integrator 102, 104 is followed by a respective sample-and-hold circuit 106, 108 and a full-wave rectifier 110, 112 or an absolute value circuit. The output signals of the full-wave rectifier circuits 110, 112 are subtracted in a subtractor circuit 114 to provide an error signal. The error signal is filtered in a low pass filter 116 to provide a control signal for a voltage controlled oscillator (VCO) 118. The VCO 118 provides an output clock signal at a terminal 120 The output clock signal at terminal 120 is provided to a timing circuit 122 which provides signals to control the timing of the two integrators 102, 104 and their respective sample-and-hold circuits 106, 108.
FIG. 2 shows the operation of the phase lock loop of FIG. 1. In the absence of any phase error and noise, the integral from the early and late integrators are equal in magnitude and the difference between the absolute value of these magnitudes is zero. Note that the relative sign of the two integrals is dependent on the bit pattern of the input data signal, but following full-wave rectification or an absolute value function, the polarity of the bit pattern of the input data signal is removed and does not affect operation of the phase detector.
In the presence of a phase error between the transition point of the two integration intervals and a data transition of the input data signal, the integration intervals are asymmetric so that the data transitions of an input data signal fall into either one of the two integration intervals. This reduces the magnitude of one of the integrated values so that the difference between the absolute value of the two integrated values is non-zero and its sign indicates the direction of the phase error.
It is desired that the end of the early integration interval coincide with the bit transition boundary and the start of the late integration interval. If some phase error exists between the bit steam and the timing of the early/late integration intervals, the loop VCO is either advanced or retarded to realign the position of the early/late gate boundary to coincide with the bit transition bounding.
Because of its relative complexity, the early/late gate phase detector has found limited application in data timing recovery. As a consequence, simpler phase detection techniques have found broader acceptance despite their poorer performance in low signal to noise ratio applications. With the rapid growth of wireless communications systems, and their inherent need to operate over a broad range of signal to noise ratios, there is renewed interest in the more robust performance that is possible with an early/late gate phase detector.